CE433 2022 Spring
Lab  2
John Hitti
jdhitti@fortlewis.edu

Lab 2

Introduction
This purpose of this lab is to introduce us to programming the FPGA using vivado. In this this lab we will create some simple AND, OR, and XOR gates in verilog that will then be used to program the FPGA.

Task 1
In this task we started by creating an AND gate.


A test bench was then created for this module and a simulation was run to verify the functionality.




Once the functionality of the gate was verified we can begin the process to upload it to the FPGA board. First, we add a constraints file to the project to specify the onboard inputs and outputs.



Then we can create a testbench that will interface directly with these inputs/outputs and our gate.


Then we can run the synthesis, implementation, and generate a bitstream file. This file is then uploaded to the board, and we can verify its functionality.



However, if the board is powered off the program will be erased. Our board features on-board memory so the board will retain the program the board when it is power cycled. To do this we need to use the generated .bin file and upload it to the board's memory. Once this is done we can verify the functionality.




Task 2
In this task we will repeat the above procedures for an OR gate and a XOR gate.

OR
We first start by coding and verifying our or gate via simulation.



We can then upload the program to the board and verify its functionality.


Once the program is verified we can upload it to the on-board memory.





XOR
We first start by coding and verifying our or gate via simulation.



We can then upload the program to the board and verify its functionality.


Once the program is verified we can upload it to the on-board memory.



Discussion
This lab was an excellent introduction to programming simple gates onto the FPGA using Vivado! This will help with future labs and project which we will use more complicated programs with our FPGA.