CE 433 Lab Spring 2022
Lab 5
Name: David Lee
Email: djlee1@fortlewis.edu

A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers

Introduction:
In this lab we use Verilog to create code that we will use in vivado to make our FPGA board function

Materials and Methods:
gvim(was used to write the verilog), Vivado and Basys 3Board

Results:

Task 1: Use Switches as the 3bit input, use LEDs to show the binary result


Figure 1: Shows the code for the Adder and Board


Figure 2: Shows the Video

Task 2: Use Switches as the 3 bit input and use the seven-segment display to show the decimal result.



Figure 3: Shows the Code used for the board and test bench


Figure 4: Shows the code for the display Part 1


Figure 5: Shows the code for the Display part 2


Figure 6: Shows a video of it working.




5. Discussion
This Lab was challenging for me to complete because I had a hard time getting the 7 segment display to do what I wanted. I was able to get the 3 bit Adder and Sub completed with easy just the display portion is what challenged me. Overall this was was able to be successfully complete and help me get a better understanding of 7 segment displays and the basys 3 board.