CE 433 Lab Spring 2022
Lab 1
Name: David Lee
Email:
djlee1@fortlewis.edu
Verilog, Vivado and FPGA Basics
Introduction:
In this lab we use Verilog to create code that we will use in vivado to make our FPGA board function
Materials and Methods:
gvim(was used to write the verilog), Vivado and Basys 3Board
Results:
Task 1: Go through all the steps in the lab, report code, simulation results and on board verifcation
Figure 1: Shows the
code written for the And Gate
Figure 2: Shows the simulation results of the AND Gate
Figure 3: Shows a picture of the And Gate Functioning on the Basys 3 Board
Task 2: Use the same procedure to create XOR and OR gates. Run Simulations
Figure 4: Shows the Verilog Code for the OR Gate Simulation
Figure 5: Shows the simulation results of the OR Gate
Figure 6: Shows the Verilog Code for the XOR Gate Simulation
Figure 7: Shows the simulation results of the XOR Gate
Task 3:
Use both the volatile and nonvolatile methods to program the FPGA.
https://youtu.be/MbcsVsjBVIg
Figure 8: This Video shows the use of nonvolatile programming since the board functions once its power cycled
https://youtu.be/M-I56c83V94
Figure 9: This Video shows the use of volatile programming since the code is not in the memory
5. Discussion
This
tutoiral was really fun and interesting to impletement. The only
section that I was struggling with was when I was trying to simulate
the XOR gate I kept getting errors stating that there was something
wrong with the leds. This was because that chunk of the constranits
file had been deleted somehow and I didn't know to check that. Once
that was fixed the code was able to be operated smoothly.