Lab1

CE338 Digital VLSI Design Lab
Lab 6 - Full Adder

Connor O'Keefe
Email: cwokeefe@fortlewis.edu

Introduction
This lab is to build the layout of a full adder using PMOS and NMOS transisters and verfiy with simulation. The full adder is composed of premade XOR, NAND, NOR, and inverter gates.

Materials and Methods

Electric VLSI
LTSpice

Procedure
Creating the NAND schematic and layout:

Creating the NOR schematic and layout:

Creating the XOR schematic and layout:

Creating the Full Adder schematic and layout:

Results
NAND Simulation:

NOR Simulation:

XOR Simulation with VDD input:

XOR Simulation with GND input:

FA Simulation with VDD input at Cin:

FA Simulation with GND input at Cin:

Discussion
All logic for each gate performed as expected. The full adder was composed of "longer" gate layouts (i.e., the NAND gate layout was extended such that it is the same height as the XOR layout).