Introduction This lab
is to build the layout of an inverter using PMOS and NMOS transisters and verfiy with simulation.
Materials and Methods
Electric VLSI
LTSpice
Procedure
The schematic is built with the PMOS drain connected to the NMOS drain
(From top to bottom as source (P) to drain (P) to drain (N) to source
(N)). With VDD connected to the PMOS source and ground to NMOS source,
input at the gates, and the output at the drains.
The layout of the inverter:
The layout of the larger trasister:
Results Simulation of the inverter:
DC INPUT
AC INPUT (PULSE)
Simulating the smaller and the larger inverters driving a capacitor with 100fF, 1pF, 10pF respectively. The smaller (20/10) inverter is on the left and the larger (100/50) inverter is on the right.
20/10 100/50 100 fF
1 pF
10 pF
Discussion The
inverter output matches the theoretical output. It is also shown that
the larger (100/50) capcitor can drive larger capacitors. The smaller
(20/10) inverter failed to drive the 10 pF capacitor while the larger
(100/50) inverter was still able to drive it.
