CE338 Digital VLSI Design Lab
Lab 2 - Design an R-2R DAC
Connor O'Keefe
Email: cwokeefe@fortlewis.edu
Introduction
The goal in this lab is to understand the operation of the ideal ADC and DAC. We will design an R-2R DAC in Electric VLSI.
Materials and Methods
Procedure
By
designing an R-2R DAC, we may replace the ideal DAC and compare both
simulations to see the results. The time delay will also be calculated
and compared to simulation.
Results
Task 1: Simulating the ideal ADC-DAC
Task 2: Design of the R-2R DAC and simulation
Task 3: Testing the time delay from the B9 pin
Time delay calculation: 0.7*R*C
= 0.7*(10k)*(10p) = 7E-8 = 70 ns
Discussion
By simulating the R-2R DAC we see it does accurately replace the ideal
DAC. The calculation of the time delay matches the simulation results.
