Introduction The
Basys 3 board will be used to impliment 1) an inverter, a 2-bit full
adder, an 8-input AND, and a 4-1 MUX, 2) perform a running LED on the
board, 3) interface with the 7-segment display to show the numbers 0-9
and 4) show the previous step with only one display on. Materials and Methods -Basys 3 FPGA
-Vivado
-gVim
Procedure Using gVim, the testbenches
and module wwere either followed or designed for the given task. The
code was then added to a Vivado simulation and/or uploaded to the FPGA.
Results
Task 1: Using
Verilog and Vivado to demonstrate the following combinational logic
blocks in both simulation and on the board (switches/leds): 1) Inverter
Fig 1. Inverter gVim Code
Fig 2. Inverter Simulation
A video demo is show below
2) 2-bit full adder
Fig 3. gVim 2-bit Full Adder Code.
Fig 4. Vivado 2-Bit Full Adder Simulation
3) 8-input And
Fig 5. gVim 8-input AND Code.
Fig 6. Vivado 8-input AND simulation.
4) 4-1 MUX
Fig 7. gVim 4-to-1 MUX Code.
Fig 8. Vivado 4-to-1 MUX Simulation.
Task 2: Perform a running LED on the Basys 3.
Fig 9. gVim Running LED Code
Task 3: Interface with the 7-segment display.
Fig 10. gVim 7-Segment Display Code with Switch Interface.
Task 4: Interact with only one of the 7-segment displays. The code here will be the same. The second video is an demo of the on board memory.
Discussion This lab
was very helpful in learning how to interact with the Basys 3 board and
simulate in Vivado. For example, we had to design testbenches for most
of the simulations and uplaods to the Basys 3.
