ENGR338 Fall 2021
8-bit SAR ADC
Name: Cheyenne Tucson
Email: crtucson@fortlewis.edu

8-bit Successive-Approzimation-Register Analog-to-Digital Converter (ADC) Simulation in Electric VLSI

1. Introduction

Knowing how a Succesive Approximation Register (SAR) operates is crucial to understanding how a SAR ADC converts a voltage sampled at a moment into a digital translation. The SAR is constructed of many D Flip-flops that have set/reset functionality. The D Flip-flop specifically used in this SAR is based off a circuit from Texas Instuments (TI) that is intended for commercial use; This flip-flop is made of 3-input NAND gates. For this assignment, a 3-input NAND gate will be laid out and simulated in Electric VLSI out of NMOS and PMOS transistors, and have a symbol created for use in other schematics. The D-Flip-flop will be built out of NAND gates, and the flip-flop will be used to build the 8-bit SAR block. Each will be simulated in LTSpice to confirm functionality before using it to build the other circuits.

2. Materials

3. Procedure

First, I converted the dimensions of the 50nm technology to C5 technology of the same resistivty. Then I created schematics for both 2 and 3 input NAND gates, a 2 input AND gate, and two different sized inverts (40/20 and 100/50 respectively) with these sizes. I made icons for each component and ran simulations to ensure everything still looked right; these can be found in PDF 1 below. Once this was done, I went ahead and converted all of the schematics given to us from LTSpice to the C5 sizes. Once this was done, I began designing the schematics in Electric VLSI.

First, I created the schematic for the Sample and Hold schematic. This schematic, the first schematic in PDF 1, contains the necessary components for a charge-pump and a low-pass filter to provide a steady V_GS to the pass gate of the sample-and-hold block. This is necessary to achieve an electric potential of 2VDD in the circuit to ensure the output is stable. Once this was complete, I created an icon view and simulated the circuit to ensure proper functionality. These results are showin with the schematic in PDF 1. The sample and hold circuit will sample the input signal, and once the clock signal has a rising edge, the sample will be tracked, and once the edge falls, the tracked value will be held until the next rising edge. This holding period is where the conversion takes place.

Next, I created the schematic for the D-Flip-flop from TI. This design has set and reset functionality. Once the schematic and icon was created and DRC clean, I simulated the circuit to ensure it worked properly. I also created a buffer out of two inverters. This is to help stabalize some signals in the SAR.

Once the D-Flip-Flop and buffer was done, I could move on to the 8-bit SAR. The SAR begins by initializing with 1 MSB. When connected to a comparator, it will intake the comparator's bit and place it in the bitstring by shifting out the original bits. This SAR requires 9 DFFs in each row, one for each bit in the bitstring and one to shift out the bits, totalling in 18 DFF blocks. This schematic and icon can be seen in PDF 1 below along with the simulation proving the functionality of the circuit.

I then laid out the schematic for the op-amp. This specific op-amp acts as a comparator. This is needed for the SAR mentioned in the paragaph above. These can also be found in PDF 1.

I then edited the 10-bit R-2R DAC from Lab 2 to create an 8-bit version. I edited the icon view as well, and I ran a simulation to check it. I simulated 00000001 to see if I got 1 LSB as the analog output. I calculated this with the equation Vin*(1/2^8), and I used 5V as the input for the simulation. The results can be seen in the PDF along with the others. We need two DACs for our simulation, but only one for functionality. The first one is for feeding into the comparator to carryout the conversion. The second one is just to verify our results from the door-register is being converted properly.

Once this was done, I needed to create the timing circuits. These were the 8-bit door register and the clock block. The clock block is just as important as the SAR to this SAR-ADC, as the components of the circuit rely on timing to be optimal/function properly. The clock block includes a 4-bit counter, to allow us to count for 12 counts, and three timing-logic circuits. These timing circuits counted to 10 for the clock-door to allow for the door register to open after the SAR shifts the output to it, counted to 11 for the Sample/Hold circuit to allow for the conversion to complete before tracking and holding another sample, and count to 12 to wait to reset the counter until the last clock update has finished. These extra counts should not affect the SAR as the output would already be sent before any more shifting could happen, as well as the same sample will be held in the positive terminal of the comparator.

The door register acts as a holding bay for the output from the SAR. This allows for more control of when the output is sent out to ensure that no bits are left behind in the conversion. This door register is made of D-Flip-flops that pass the input straight to Q, and is waiting for the clock to trigger it to release the value. I created icons for both components, and then I ran simulations for each as well. These can be found in PDF 1 below.

After all these schematics came out DRC clean, and the simulations showed satisfactory results, I laid out the schematic for the SAR-ADC. Once this was DRC clean, I simulated the circuit with a clock that had a 10% duty cycle. This was to ensure a decent resolution. These can be found in PDF 3.

Once the final simulation was complete, I exported the voltage data as a text file and created a python script to calculate the INLs and DNLs and plot the data. These can be seen in Figures 1,2, and 3 below.

I also wrote code to calculate all of the various values needed to fill out the specification table seen below in Figure 4. There are two values missing. I need to speak with Dr. Li for some clarification before I include those figures in the script.


4. Results

The numbers represented in Figure 1 are from a transient analysis; the values were extracted starting at 0V signal input up to 5V signal input. The results for the INLs and DNLs were done using the average output values found for inputs within a tolerance of the ideal analog voltage for that particular bitstring. The allotted tolerance was 1/8 of a LSB, in this case it was 2.4414 mV. This was done to condense the data to a more manageable time frame for the script to render the graphs.

PDF 1. This is a PDF with the screen-snips of the components of the SAR-ADC in the converted C5 sizes. All DRC checks and simulation results are shown with their schematics in the respective order as mentioned in this report.
PDF 3. This is a PDF of the SAR-ADC schematic and simulation result!


Figure 1. A graph of the actual voltage outputs (black) vs ideal voltage outputs (purple) of this ADC for the same input voltage. Results were taken from a simulation ran with a 15% duty cycle, and data from cycles in transition periods were removed to have the results reflect performace during use.
Figure 2. A graph of the calculated DNLs of this ADC. Results were taken from a simulation ran with a 15% duty cycle, and data from cycles in transition periods were removed to have the results reflect performace during use.
Figure 3. A graph of the calculated INLs of this ADC. Results were taken from a simulation ran with a 15% duty cycle, and data from cycles in transition periods were removed to have the results reflect performace during use.
Figure 4. A screen-snip of the specification results for this particular ADC. Results were taken from a simulation ran with a 15% duty cycle, and data from cycles in transition periods were removed to have the results reflect performace during use.

5. Discussion

From the example report provided to us, the simulation results look different from Dr. Li's simulation because the clocks were ran at different duty cycles. The resolution is higher in Dr. Li's simulation than in the one seen in the sample report by Audra Benally.

The huge dip in the output is only because it starts at 0V instead of the same voltage of the beginning input value, and it takes time to start the conversion process. This small delay is what is causing the dip in the output signal, and it does not mean that the ADC is useless!

Eventhough the output looks very similar to the output of the sample-and-hold component, we need the rest of the circuit to actually do the conversion. The output from the sample-and-hold is still an analog value and not translated to an 8-bit bitstring. The reason they look so similar is because of the second DAC in the circuit. This is only to verify the conversion. The actual converted result is a parallel output.

This project was great! It really reinforced my understanding of how a SAR-ADC works, and it also gave me a lot more practice with SPICE simulation and laying out/reading AOI schematics. It also was nice practice in converting circuits. I really enjoyed this project.