ENGR338 Fall 2021
Lab 9: Design a Simple 8-bit ALU in Electric VLSI
Name: Cheyenne Tucson
Email: crtucson@fortlewis.edu

Design a Simple 8-bit Arithmatic Logic Unit (ALU) in Electric VLSI

1. Introduction

ALUs are a building block for many different applications of digital circuits. During the completion of this lab, a simple 8-bit ALU will be be designed and laid out in Electric VLSI.

Before I could begin, I had to catch up and complete the layouts I didn't allow time for in the previous lab. To do this, I drew a stick diagram of the 1-bit Full Adder to restart my layout over to ensure I recieved clean NCC checks this time. This is shown in Figure 1 below. The AOI circuit diagrams for these stick diagrams can be found in PDF 1.

Figure 1. This is a stick diagram of the 1-bit Full Adder I designed. The circuit on the left is the circuit for the Carry-out bit, and the circuit on the right is for the solution bit. Gates with input A are highlighted in blue, Gates with input B are highlighted in green, and Gates with the Carry-in input are highlighted in orange. The pink highlighting is for NOT-Carry-out, and the purple highlighting is for NOT-Solution. The yellow highlighting indicates both Carry-out (left) and Solution (right) outputs.

The layouts of both the 1-bit and 8-bit versions of the Full Adders as well as the simulations confirming the 8-bit version's functionality can be seen below in PDF 1. Note that I used metal layers to make the longer gate connections to limit use of poly-silicon wires. My thinking behind this is to remove as much possible resistance in this high-speed design. Once this lab is graded, I will update the content of both lab pages accordingly.

PDF 1. This PDF contains screen-snips of all the steps I wasn't able to complete of lab 8 before the due date. All schematics, Icon views, Layout views, error check results, and the simulation results for the 8-bit version are shown in order of the tasks outlined in the instructions for lab 8.

2. Materials



3. Procedure

After catching up with my Full Adder, I created the schematic, icon, and layout views for an 8-bit version of the 20/10 Inverter, and I ran a simulation in LTSpice to confirm the logic was still accurate. Next, I created a schematic for a simple 8-bit ALU. I then ran a series of simulation in LTSpice to confirm the functionality of the AND and OR gates within the ALU, and then I ran a simulation to confirm the functionality of the adding and subtracting operations. These simulatons, along with the schematic and layout views of the 8-bit inverter with respective error check results, can be found in PDF 2 below.

I then laid out the physical design of the simple 8-bit ALU and ensured there were no errors with a DRC, NCC, and wells check. I made a diagram of how I planned to design the layout before I began in Electric. These can all be found in PDF 2 also.

4. Results

PDF 2. This PDF contains screen-snips of all steps of this lab. All drafting diagrams, schematics, icon views, layout views, simulation results, and error check results are shown in order of the tasks outlined in the lab instructions.

5. Discussion

I'm glad I was able to finally catch up with everything nicely during this last lab. I designed two different layouts because the first time, I was planning as I went. My first design did not come out NCC clean (labeled Design 2 in the PDF), and there were so many that I decided to start over. With the second design (Design 1 in the PDF), I drew a quick sketch of where I wanted to place my outputs and my components. This and keeping everything spaced out until the very end made designing the layout for the ALU easier, less time consuming, and with less errors along the way than it did with the first design I didn't plan out. This lab was great practice with organization and with designing the layouts. I think the design I came up with would have a decent yield if this were to be fabricated. I tried to keep the spacing as minimal as possible, and the design can be arranged to fit more circuits on the wafer.

I really enjoy these labs. Even though they are time consuming, I enjoy designing these layouts.