Vann
Montoya - Computer Engineer - Fort Lewis College
bvmontoya@fortlewis.edu
2023 Fall
CE338L - Digital VLSI Design Lab
Lab 1: (Completed)
Review Superposition, Thevenin's Equivalent Circuit, and LTSpice
Lab 2: (Completed)
Design an R-2R DAC
Lab 3: (Completed)
Layout the R-2R DAC
Lab 4: (Completed)
MOSFETs and IV Curves
Lab 5: (Completed)
The Interter
Lab 6: (Completed)
Build a NAND, NOR, XOR, and Full Adder
Lab 7: (Completed)
Using Buses in ElectricVLSI
Lab 8: (Completed)
Design a MUX, and a High-Speed Full Adder
Lab 9: (Completed)
Design an 8-Bit ALU
Course Project: (In Progress)
8-Bit SAR ADC
2023 Spring
CE351 - Microcontrollers
Assignment 1: (Completed)
PowerModulePCB
Assignment 2: (Completed)
Heart Rate and Blood Oxygen Saturation Monitor
Assignment 3: (Completed)
LCD's, Sensors, and Actuators
Assignment 4: (Completed)
PID Control with Photocells
Assignment 5:
Four-Wheel Smart Robot Car
Assignment 6: (Completed)
Build an IoT temperature monitor
Assignment 7: (Completed. Mostly...)
ESP32 WiFi-BT-BLE MCU Module
CE433 - Embedded Devices
Report 1: (Completed)
Verilog and FPGA Basics
Report 2: (Completed)
Data Types, Operators and Combinational Logic
Report 3: (Completed)
Combinational Logic Blocks
Report 4: (Completed)
Data Storage Units
Report 5: (Completed)
Sequential Logic
Report 6: (Completed)
Video Graphics Array (VGA)
Report 7: (Completed)
Universal Asynchronous Receiver/Transmitter (UART)
Report 8: (Completed)
Embedded Soft-Core
Report 9: (Completed)
Universal Serial Bus (USB)
Report 10: (Completed)
Serial Peripheral Interface (SPI)
CE433L - Embedded Devices Lab
Lab 1: (Completed)
Vivado, gVim Installation and Preparation
Lab 2: (Completed)
Verilog, Vivado, and FPGA Basics
Lab 3: (Completed)
More About FPGA - Seven Segment Display and More
Lab 4: (Completed)
Combinational Blocks
Lab 5: (Completed)
2's Complement Adder
Lab 6: (Completed)
Basys 3 and VGA
Lab 7: (Completed)
Basys 3 and LCD Display
Lab 8:
The PicoBlaze Softcore