CE338 Lab 2020 Spring
Lab 4
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu
1. Lab 3 - MOSFETs and IV Curves
2. Introduction
The purpose of
this lab was to be able to build these MOSFETs in Electric VLSI and be able to analyze the IV curves of those MOSFETs.
3. Materials and Methods
The below schematics and layouts show how the MOSFETs were built in
Electric VLSI as well as the spice code used to produce the results. All of the schematics were DRC/ECC error free, and the schematics were NCC error free as well.
Figure 1. Layout of NMOS
Figure 2. Schematic of NMOS
Figure 3. Layout of PMOS
Figure 4. Schematic of PMOS
4. Results
The final results from running the simulation for the above
schematics are shown the below figures.
Figure 5. Results from Spice Simulation of NMOS Layout
Figure 6. Results from Spice Simulation of NMOS Schematic
Figure 7. Results from Spice Simulation of PMOS Layout
Figure 8. Results from Spice Simulation of PMOS Schematic
5. Discussion
This lab
let us create our own custom 4-port MOSFETs and then test them to
ensure that they were working. The tutorial made it clear that these
may be used in future projects. Given that, testing the IV curves and
getting error free schematics and layouts was essentail in this lab to ensure good resources for future labs.
