CE338 Lab 2020 Spring
Lab 3
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu

1. Lab 3 - Layout the R-2R DAC

2. Introduction
The purpose of this lab was to gain a better understanding of the layout system and the use of subcells in Electric VLSI using our previously gained understanding of the R-2R DAC.

3. Materials and Methods
Task 1:
The first task was to create the schematic for the subcells of the R-2R ladder. The ladder was broken up by bits connected to three series resistors with exports before the first, after the last, and in between the second and third resistors to mimic our formerly created R-2R schematic as seen in Figure 1.
Figure 1. Schematic of R-2R Ladder Subcells

These subcells were then layed out together to form the entire R-2R ladder as seen in Figure 2.
Figure 2. Schematic of R-2R Ladder

Task 2:
The second task was to create layout views for the new schematics. Figure 3 shows the layout for the R-2R ladder subcells.
Figure 3. Layout of R-2R Ladder Subcells

This subcell layout was then implemented into the R-2R ladder layout and an array modifier was used to give ten copies with equal spacing to avoid DRC and NCC errors as shown in Figure 4.
Figure 4. Layout of R-2R Ladder

This final design, which had no DRC or NCC errors, was then assumed to be correct if our original schematic interacted well with the given Ideal ADC. So, a new simulation file was made and the new R-2R ladder was added as seen in Figure 5.
Figure 5. ADC/R-2R DAC Final Testing Schematic


4. Results
The final results from running the simulation for the above schematic are shown below in Figure 6. The newly designed R-2R ladder functioned well, so it can be assumed that our DRC and NCC error free layouts are functional.
Figure 6. ADC/R-2R DAC Final Testing Simulation Output

5. Discussion
This lab introduced us to the concept of layouts in Electric VLSI and built upon the previous labs themes of designing and R-2R Ladder to reinforce those concepts. Subcells and other tools such as the array modifier also seem like a great resources for designing repeating structures in Electric VLSI.