CE338 Lab 2020 Spring
Lab 2
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu
1. Lab 2 - Design R-2R DAC
2. Introduction
The purpose of this lab was to design a funtional R-2R DAC inside of
Electric VLSI. We tested this R-2R DAC to ensure it was working
properly, and then found the time delay from the B9 pin when driving a
10pF load.
3. Materials and Methods
In this lab, we were given an ideal ADC/DAC schematic to work from. The schematic view of these files can be seen in Figure 1.
Figure 1. Given Ideal ADC and DAC for testing purposes
4. Results
Task 1:
For
the first task we were asked to run a simulation on the given ideal ADC
and DAC to ensure the software was working correctly. That simulation
can be seen in Figure 2.
Figure 2. Results from Ideal ADC/DAC Simulation
Task 2:
For
the second task we were asked to redesign the R-2R DAC and repeat the
simulation to ensure it was working properly. The completed R-2R DAC
can be seen in Figure 3.
Figure 3. Schematic of R-2R DAC with Completed Icon
The next task was to wire it into the existing circuit as seen in Figure 4 and rerun the simulation as seen in Figure 5.
Figure 4. Schematic of R-2R DAC integrated into Ideal Circuit
Figure 5. Results from R-2R DAC Simulation
Task 3:
The final task
was to find the time delay of B9 if all other pins were grounded and
the circuit was driving a load of 10pF. The circuit for this test can
be seen in Figure 6.
Figure 5. Schematic of Testing Scheme for B9 Time Delay
The final results of this task were wrong. There is meant to be a curve
on the Vout signal which we can test to find the time delay. However
due to some artifact on Electric VLSI the capacitor wasn't acting as a
sink but instead routed all of the power straight to ground. Therefor,
we are getting 2.5V on the original Vout line, but the labeled Vout
line in the above schematic doesn't give off any power. The simulation
can be seen in Figure 7. The supporting hand calculations can be seen
in Figure 8.
Figure 7. Results from B9 Time Delay Simulation
Figure 5. Supporting Hand Calculations for B9 Time Delay
5. Discussion
This lab
was a great introduction to Electric VLSI and ADC/DAC's. The R-2R
ladder has a simple implementation that more allowed for me to get
familair with the software than have to fight
the circuit. The failed simulation results from the final task is
something I'll have to learn from going forward, and allow more
allotted time to deal with bugs like this.