ENG338 Lab 2020 Spring
Lab 7
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu
1. Lab 7 - Using Buses in ElectricVLSI
2. Introduction
The purpose of this lab was to use buses in Electric VLSI to deal with
arrays of components. Buses are used to simplify these circuits for
testing purposes.
3. Results
Task 1:
This task asked us to create a 2:1 MUX and then use buses to make it an 8-bit MUX. All of the Below Schematics are DRC and NCC error free.
Figure 1. 2:1 MUX Schematic
Figure 2. 2:1 MUX Simulation
Figure 3. 2:1 MUX Layout
The 8-bit MUX is
shown below. This was converted from the 2:1 MUX using buses and by
arraying and connecting the layout of the 2:1 MUX.
Figure 4. 8-bit MUX Schematic
Figure 5. 8-bit MUX Simulation
Figure 6. 8-bit MUX Layout
Task 2:
This task asked us to create a high speed full adder using only
transistors which are space saving compared to using logic gates. This
becomes significant when we make an 8-bit adder in Task 3. The NCC
Error in Figure 10 shows the error that stopped these schematics from
being NCC Error free. They are all DRC Error free.
Figure 7. Full Adder Schematic
Figure 8. Full Adder Simulation
Figure 9. Full Adder Layout
Figure 10. NCC Errors from 8-bit Full Adder
Task 2:
This task asked us to array the previously created Full Adder to
create an 8-bit High Speed Full Adder. These schematics suffer from the
same NCC errors as the original Full Adder but other than that are
error free.
Figure 11. 8-bit Full Adder Schematic
Figure 12. 8-bit Full Adder Simulation
Figure 13. 8-bit Full Adder Layout
4. Discussion
This lab
was a great introduction to the utility of minimizing the space used
when designing advanced circuits. Using transistors to create the Full
Adder saved a significant amount of space but added complexity to
designing the circuit.
