ENG338 Lab 1

ENG338 Lab 2020 Spring
Lab 7
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu

1. Lab 7 - Using Buses in ElectricVLSI

2. Introduction
The purpose of this lab was to use buses in Electric VLSI to deal with arrays of components. Buses are used to simplify these circuits for testing purposes.

3. Results
Task 1:
This task asked us to create a ring oscillator using inverters. All of the below are DRC and NCC error free.

Figure 1. Original Ring Oscillator

Figure 2. Bus Ring Oscillator

Figure 3. Ring Oscillator Layout

Task 2:
This task asked us to create an 8-bit AND gate, using buses to help us implement it. In order to do this we had to create a singular AND gate. Figure 1 and Figure 2 show the schematic and layout respectively, from that AND gate. All of the below are DRC and NCC error free.

Figure 4. AND Gate Schematic

Figure 5. AND Gate Layout

Figure 6. 8-bit AND Gate Schematic

Figure 7. 8-bit AND Gate Simulation 1

Figure 8. 8-bit AND Gate Simulation 2

Figure 9. 8-bit AND Gate Layout

Task 3:
This task asked us to create an 8-bit OR gate, using buses to help us implement it. In order to do this we had to create a singular OR gate. Figure 1, Figure 2, and Figure 3 show the schematic, layout, and verifying simulation respectively, from that OR gate. All of the below are DRC and NCC error free.

Figure 10. OR Gate Schematic

Figure 11. OR Gate Layout

Figure 12. OR Gate Verifying Simulation

Figure 13. 8-bit OR Gate Schematic

Figure 14. 8-bit OR Gate Simulation

Figure 15. 8-bit OR Gate Layout

Task 4:
This task asked us to create an 8-bit NAND gate, using buses to help us implement it. All of the below are DRC and NCC error free.

Figure 16. 8-bit NAND Gate Schematic

Figure 17. 8-bit NAND Gate Simulation

Figure 18. 8-bit NAND Gate Layout

Task 5:
This task asked us to create an 8-bit NOR gate, using buses to help us implement it. All of the below are DRC and NCC error free.

Figure 19. 8-bit NOR Gate Schematic

Figure 20. 8-bit NOR Gate Simulation

Figure 21. 8-bit NOR Gate Layout

4. Discussion
This lab was a great introduction to the utility of bus arch's in Electric VLSI. Making connections and running wires via the bus is a much simpler way to deal with arrays of components. The layouts of these components were harder, as they had to be arrayed manually. This led to many DRC errors as the individual layouts weren't originally built to be arrayed and had to be manipulated until the arch's could run without getting to close to one another (mainly the Metal-1 connections).