ENG338 Lab 2020 Spring
Course Project
Name: Braden Morrow
Email: bdmorrow@fortlewis.edu
1. Course Project - Design and Validate an 8-bit SAR ADC
2. Introduction
The course project asked us to implement a schematic of an 8-bit SAR ADC in Ltspice. The SAR ADC takes in an
analog voltage and outputs its digital equivalent. The accuracy of this
device goes up as the output bits go up, so we were asked to design an
8-bit SAR rather than the 4-bit SAR pictured in the course project
outline. In
order to do this, we had to design and verify the 3-bit NAND gate and
TI-DFF that act as the main components in the SAR ADC. This
project also used the 50nm technology that was given at the beginning
of the semester. Therefor, the entire circuit runs on 1V VDD.
3. Results
Task 1:
This task asked us to create a 3-bit NAND gate that
was used to create the TI-DFF in Task 2. The 3-bit NAND gate should
only show HIGH on the output when all three inputs are HIGH, as shown
in figure 2.
Figure 1. 3-bit NAND Schematic
Figure 2. 3-bit NAND Simulation Results
Task 2:
This task asked us to create a TI-DFF using the
3-bit NAND gates from Task 1. The simulation for the TI-DFF is
pretty simplistic and just shows that the output Q mimics the input
Data on each rising edge of the clock cycle unless the Set and Reset
pins are set to HIGH.
Figure 3. TI-DFF Schematic
Figure 4. TI-DFF Simulation Results
Task 3:
This task asked us to implement the TI-DFF into the SAR Block circuit and verify its outputs. Due to the simulation just using an alternating comp input in the updated course project, the logic of the SAR ADC was easy to test. The hand calculations show that the the
final output of the state machine matches what we would expect from an
alternating comp beginning with LOW and that the SAR ADC is working.
Figure 5. SAR ADC Schematic
Figure 6. SAR ADC Simulation Schematic
Figure 7. SAR ADC Simulation Results
Figure 8. Hand Calculations to Verify Output
4. Discussion
This
course project provided a unique opportunity for us to test a more
complicated component that we conceptualized in class. Being able to
apply the state machine calculations to actually verify the output of
the SAR ADC was a great way to apply the theory we learned in class.
This project also allowed us to experiment with 50nm technology in
LTspice. The overall results and circuit was the same as it would be
for the technologies we used previously, however it was interesting to
see how changing two transistor sizes can allow entire components to be
run on differen't input voltages.
