CE433 Embedded Systems
Tutorial 3: Combinational Logic Blocks
Name: Audra Benally
Email: albenally1@fortlewis.edu

1. Title: Combinational Logic Blocks

2. Introduction: This tutorial provided more practice with coding in verilog. Different combinational logic blocks were reviewed and implemented with Vivado and the FPGA. New coding techniques were also demonstrated in verilog.

3. Materials and Methods:
        Materials:
                 - Computer
                 - Vivado Software
                 - GVim Software
        Methods:
             For each of these tasks the tutorial provided appropriate directions. In several, a testbench needed to be coded and the simulation was then performed. The tutorial became more technical as the tasks went on and the end tasks were re-build past tasks with ideas from the combinational logic block experiences.

4. Results:

   
             Figure 1. Half Adder simulation.

   
             Figure 2. Full Adder simulation

   
             Figure 3. One bit comparator files and simulation.

   
             Figure 4. 4 bit comparator files and simulation results.

   
             Figure 5. A two to four decoder files and simulation results.

   
             Figure 6. Eight to three encoder file and simulation results.

   
             Figure 7. 4-1 MUX files and simulation results.

   
                Video 1: 4-1 MUX implemented on the Basys 3 board.
    Video link: https://youtu.be/wWwkpatrT_c

   
             Figure 8. Three bit even parity generator file and simulation.

   
                Video 2. Even parity generator implemented on the Basys 3 board.
    Video link: https://youtu.be/n1Yk8Z4TFB0

   
             Figure 9. Even parity checker file and simulation results.

   
                Video 3. Even parity checker implemented on a Basys 3 board.
    Video link: https://youtu.be/SZnVavtykiY


5. Discussion
    For this tutorial, the logic gates were interesting to create. I enjoyed relearning about the logic gates that I vaguely remembered from fundamentals of logic. This tutorial provided great practice for verilog. I did not finish this lab. I am missing the 2 bit comparator and the last task for the home alarm and the car parking spot system. I have an issue where the Vivado software will pretty much stop working because it will load for a very long time. I usually use the task manager to force the softare to stop (the longest I've waited is about 30 minutes) and I can't even open a file without the loading window taking forever again. I'm not sure what the issue is. I've only gotten it to stop by deleting source files but that method is not working this time. I was working on the last task when this issue occurred again.