1. Title: Combinational Logic Blocks 2. Introduction: In this lab two combinational blocks were
designed, simplified, simulated and then implemented on the Basys 3
board.
3. Materials and Methods:
Materials: - Computer - Vivado Software
- GVim Software
- Basys 3 board and cable
Methods:
For the first task we were
challenged with creating a traffic light system given the phases of a
traffic light in a figure. First a truth table was created using three
inputs. Then logic equations were derived using K maps from the truth
table. These equations were simplified then typed up in verilog. The
source files were placed in vivado and simulated. Once simulations were
correct, the files were implemented on the Basys 3 board. The second
task followed a similar path except the parity generator and checker
were already made from a past assignment. The verilog file just called
upon those past files and combined the two components in one file using
wires.
Video 1. Traffic light logic
gates implemented on the Basys 3 board using switches for the different
states.
Video link: https://youtu.be/DMG8XJH8nsQ
Task 2: Design models of one even parity generator and one even parity checker.
Figure 3. The
parity generator and checker files and simulation results.
Figure 4. The
parity checker and parity generator files used in the above file.
Video 2. The above parity
generator and checker implemented on the Basys 3 board.
Video link: https://youtu.be/Mkg75CuzDeM
5. Discussion The first task went smoothly and simulted correctly without issue. I used the parity checker and generator from tutorial #3 in this tutorial for task #2.
I wasn't very sure about how to show the inner workings of the second
task, because the parity generator works correctly so the parity
checker never has any issues. Because of this, the output is never
triggered so I hope what I showed was enough.
