2. Introduction: For this lab we will create files for three different
logic gates. These gates were the OR gate, the AND gate, and the XOR
gate. All three gates have design, testbench, and FPGA files. Each gate
will be tested with a simulation testbench before being programmed with the
testbench FPGA file.
3. Materials and Methods:
Materials: - Vivado
- Computer
- Kompozer
- Filezilla
- Tutorial References Methods:
For this lab, I started with the
OR gate files. The design file and testbench file were created using
vivado. Then the gate was simulated, the results are shown in figure 1
below. After the simulation was successful, a new testbench_FPGA file
was created that connected the inputs to switches and the outputs to a
led. Results of all four states are shown in figure 1. After the first
program worked, the FPGA was programmed using the on-board memory and
.bin file. Results are shown in video 1 where you can see the logic
gate in action before and after the power was turned off. The next two
logic gates were made in the same fashion. Results can be seen below.
4. Results:
Figure 1. OR Gate files, simulation, and FPGA results.
Video link: https://youtu.be/ZkZJY79y32w
Video 1. Nonvolatile OR gate
Figure 2. AND gate files and FPGA results.
Figure 3. XOR files
5. Discussion
In this lab, the first logic gate I made was the OR gate and it went
seamlessly. The simulation worked easily and the FPGA was easily
programmable. The AND gate was a little trickier because I could not
get the non-volatile programming method to work. The "Add Configuration
Memory Device..." option was not clickable. I was not able to spend as
much time on this lab as I had hope to. I planned to finish it today
(due day) but my Vivado program is not loading anything properly, and
also had a very long update that did not fix the non-loading issue.
When trying to replace the AND gate FPGA testbench the loading window
sits at 1% without moving. Because of these reasons and my own
procrastination due to poor time management, I was unable to record the
AND gate simulation and the XOR gate FPGA programming. I also was
unable to program the AND gate and XOR gate using on-board memory.
