ENGR338 2017
Lab 3: The Inverter/IV Characteristics of NMOS/ PMOS

James Greene
Student ID: 900396341


Buidling an Inverter with a CD4007 IC

     Inverters are a component of logic gate circuits that are capable of taking a binary input and outputting the opposite value. Many logic gates are comprised of an inverter attached to the end of an additional logic gate circuit. The NOT logic gate is constructed soley from an inverter. In this lab, an inverter was constructed from a PMOS and an NMOS transistor contained in a CD4007 IC chip, a schematic of which is shown in Figure 1.



Figure 1: Wiring Schematic of a CD100 IC.


Inverters are equipped with a threshold, or a minimum required voltage, before they will perform their function. To observe this switching point of the inverter, a power source was connected into the input of the inverter and manually sweeped from 0 to 5 volts.The resulting output voltage was monitored using a multimeter, and the switching point was observed when the gate voltage equiled the output voltage of the inverter. This occured at a gate voltage of 2.34 volts, and an output voltage of 2.38 volts. A multimeter was used to measure this switching point, because oscilloscopes are intended to plot a signal over time, and would not be appropriate to measure the two converging voltages. 


A function generator was configured to input a square voltage wave into the PMOS-NMOS inverter circuit, and an oscilloscope was used to measure the propagation delay of the inverter. The cursors were placed on the inverter signal at the location where the square input wave first induced the inverter voltage switch, and at the location where the voltage reached 50 % of the VDS. The propagation delay from low-to-high (tPLH) was determined to be 23.2 nanoseconds, as seen in Figure 2. The propagation delay from high-to-low (tPHL) is shown in Figure 3, and was determined to be 16.4 nanoseconds.


Figure 2: tPLH of the Inverter.




Figure 3: tPHL of the Inverter.


   To further explore the function of the CMOS transistors, a circuit was constructructed with an NMOS transistor from the CD4007 IC. Figure 4 demonstrates the output of the NMOS switching from high to low as the gate voltage was increased to above the threshold of the transistor. In this figure, the output current is graphed as a function of this input gate voltage. To sample this current, a 10k ohm resistor was connected between the VDS and the drain lead of the NMOS.


Figure 4: ID vs. VGS, NMOS Shifting Output from High to Low.


     Lastly, the effect of a varying the drain-source voltage on the output current was observed in the NMOS circuit. For this experiment, a 100 kohm resistor was placed between the source lead and ground. The result is shown in Figure 5, and demonstrates the linear and saturation regions of the NMOS transistor.When utilizing a transistor in a circuit, it is necessary to operate only within the saturation region. This is the region where the ID vs. VDS curve begins to flat line, and the NMOS will output the complete desired current. This procedure provides one method for experimentally observing the linear and saturation region of a CMOS transistor.


Figure 5: ID vs. VDS Linear and Saturation Region of an NMOS Transistor.




For complete instructions on how to perform these experiments, please visit: http://www.yilectronics.com/Courses/ENGR338L/ENGR338L_2017f/Lab3_Inverter-NMOS-PMOS/Lab3.html